Common interfaces of serial bus utilize clock signals by two signal control lines, serial data line (SDA) and serial clock line (SCL), to connect master and slave devices and perform the data transmission between the multiple integrated circuits or chips. I2C (inter-integrated circuit) connection is an example of the interfaces. Conventionally, the master and slave devices in the I2C system can control the level of the clock line that connected to the master and slave device directly to produce the clock signals with high/low level and perform synchronous clock controlling of data communication between the master and slave device. However, some electronic devices like an electrically erasable programmable read-only memory (EEPROM) are limited to the number of available addresses. The limitation leads that the addresses may be insufficient to support the system including a plurality of the electronic device as the slave devices, and causes failures such as double addressing or address conflict. To deal with this problem, a switching device was used to switch the connection between the master and slave devices, but an additional device, the switching device, brings about a burden of cost and a much complex design of circuit. Moreover, if the switching device is added between the master and slave devices, the clock controlling may fail to be synchronous between the master and slave devices.
The reason why the asynchronization occurs between the master and slave devices is that original direct connection of the clock line between the master and slave devices is interrupted by the participation of the switching device. The interruption causes that the master device cannot distinguish if the slave device is in service or not via the clock line directly. So, it is in need to develop a new control method for the clock signals.